1. Technical Field
The present invention relates to a semiconductor device, a microcomputer, and electronic equipment.
2. Related Art
Formerly, in the bus interface for accessing data associated with an address, as used in a memory, a bus master outputs the value of an absolute address into an address bus to perform the interface function. Either a parallel bus or a serial bus performs the same operation for the output of an absolute address.
The parallel bus has a problem that the number of address signal lines increases as the memory space accessed expands, resulting in increases of cost and electric power consumption.
The former techniques read consecutive memory data by a burst access to memory, and use this burst access together with a command queue and a cache, thereby improving the efficiency of the memory access.
These methods, however, involve high cost hardware. In addition, there is a problem that fetched data may be wasted when the program branches.
The techniques such as time-division output of addresses and data, and interfacing by the use of a serial bus are used. The serial bus, however, requires a clock cycle corresponding to the number of bits in the address for the output of the address, and therefore there is a problem that the time needed for the bus access increases.
In order to improve the transfer efficiency of the bus in the former serial bus, such a burst access as to transfer the data in an arbitrary address range from the base address is used. However, there is a problem of decreasing of data transfer efficiency when the address of instruction executed by a central processing unit (a CPU) is branched and in the data access to a random address.
The present invention addresses the above described problems and is intended to provide a semiconductor device, a microcomputer, and electronic equipment that enable the access time to be shorten at low cost with low electric power consumption.